The generation of three-dimensional graphical images is of interest in a variety of electronic games and other applications. Conventionally, some of the steps used to create a three-dimensional image of a scene include generating a three-dimensional model of objects to be displayed. Geometrical primitives (e.g., triangles) are formed which are mapped to a two-dimensional projection along with depth information. Rendering (drawing) primitives includes interpolating parameters, such as depth and color, over each two-dimensional projection of a primitive.
Graphics Processing Units (GPUs) are commonly used in graphics systems to generate three-dimensional images in response to instructions from a central processing unit. Modern GPUs typically utilize a graphics pipeline for processing data. FIG. 1 is a prior art drawing of a traditional pipeline architecture which is a “deep” pipeline having stages dedicated to performing specific functions. A transform stage 105 performs geometrical calculations of primitives and may also perform a clipping operation. A setup/raster stage 110 rasterizes the primitives. A texture address stage 115 and texture fetch 120 stage are utilized for texture mapping. A fog stage 130 implements a fog algorithm. An alpha test stage 135 performs an alpha test. A depth test stage 140 performs a depth test for culling occluded pixels. An alpha blend stage 145 performs an alpha blend color combination algorithm. A memory write stage 150 writes the output of the pipeline.
The traditional GPU pipeline architecture illustrated in FIG. 1 is typically optimized for fast texturing using the OpenGL® graphics language. A benefit of a deep pipeline architecture is that it permits fast, high quality rendering of even complex scenes.
There is an increasing interest in utilizing three-dimensional graphics in wireless phones, personal digital assistants (PDAs), and other devices where cost and power consumption are important design requirements. However, the traditional deep pipeline architecture requires a significant chip area, resulting in greater cost than desired. Additionally, a deep pipeline consumes significant power, even if the stages are performing comparatively little processing. This is because many of the stages consume about the same amount of power regardless of whether they are processing pixels.
As a result of cost and power considerations, the conventional deep pipeline architecture illustrated in FIG. 1 is unsuitable for many graphics applications, such as implementing three-dimensional games on wireless phones and PDAs.
Therefore, what is desired is a processor architecture suitable for graphics processing applications but with reduced power and size requirements.